1. Technical Field
The present invention relates to implementations of orthogonal narrowband channels in a digital demodulator, and more particularly, relates to a methodology to adapt a multi-rate processing algorithm and channel spacing of an existing channelizer design for implementation of orthogonal narrowband channels of different input data rates and input channel group bandwidths.
2. Related Art
Generally, multi-channel wireless communication systems such as satellite communication systems may contain a certain number of transponders for communications over a broad geographical area. Each transponder may be a receiver-transmitter pair. The receiver of a satellite system may be a wideband receiver that may cover a wide range of communication frequencies within an available multi-channel bandwidth. The range of communication frequencies may depend on the number of channels the satellite communication systems can handle. Channelizers may be used to separate an input wideband signal of a specific spectrum received from an antenna into a plurality of narrower band channels for further processing. The wideband signal may carry different channels using different frequency bands, different time slots, different spread spectrum coding, or a combination of any two or more of these techniques. The channelizers may be considered as wideband channelizers and/or narrowband channelizers used to separate an input wideband signal into smaller sections of constituent channels. The term xe2x80x9cwidebandxe2x80x9d may not be limited to any particular spectral range. Rather, wideband may imply a spectral coverage of at least the useful communication range over which the multi-channel wireless communications system may operate. Narrowband may, on the other hand, imply only a portion of the spectrum, for example, the width of an individual channel. Narrowband channels may be referred to as subchannels of a channel group. For example, a 15 MHz channel group may contain 50 narrowband channels each with a 300 kHz bandwidth. Many channelizers may operate on radio frequency (RF) or baseband, analog or digital signals.
Typically, multiple levels of channelization are required to access the data in the narrowband channels. However, the channelizers are typically designed for a specific channel group bandwidth and data rate set that depends on the arrangement of the prior levels of channelization. Several methodologies for typical channelizer designs are known. For example, theoretical basis for such a channelizer design is described in xe2x80x9cMultirate Digital Signal Processingxe2x80x9d by R. E. Crochiere and Rabiner, published in 1983 by Prentice Hall, Englewood Cliffs, N.J., which publication is incorporated herein by reference in its entirety. Theoretical basis for multichannel demodulator designs is provided in xe2x80x9cNarrowband Channel Group Multichannel and Multimode Demodulatorxe2x80x9d by Russell R. Rhodes and Dean P. Kolba, published in August 1997 by MIT Lincoln Laboratory. Additional basis for orthogonal narrowband channel spacing of such demodulator designs is described in xe2x80x9cOrthogonal Spacing For Narrowband Channels In The Advanced EHF Waveformxe2x80x9d by Mark Maleski et al., published in September 1997 by Booz-Allen and Hamilton. However, many contemporary channelizer designs are afflicted with considerable design constraints. Examples of the design constraints may include the following: the input data rate must be the same as the input channel bandwidth; the discrete Fourier transform (DFT) size must be the same as the number of valid output channels; and the input bandwidth must be full with valid channels. Moreover, once a channelizer design is realized for a specific channel group bandwidth and data rate set, such a channelizer may not be reconfigured and/or adapted for operations with different input data rates and input channel group bandwidths. Consequently, contemporary methodology for typical channelizers is not flexible for use in multiple data rate applications. Accordingly, there is a need for a uniform and reliable methodology used to adapt a multi-rate processing algorithm and channel spacing of a channelizer design and to develop a channelizer architecture for implementation of orthogonal narrowband channels of different input data rates and input channel group bandwidths. Such a methodology must be flexible and maintain the ability to reconfigure channelization process to account for changes in channel layout and data rate.
In accordance with the present invention, an innovative channelizer design methodology is provided to design a single orthogonal channelizer for implementation of orthogonal narrowband channels of different input data rates. The channelizer design methodology includes obtaining information relating to an input sampling rate, an input channel group bandwidth, a number chips per hop which varies in accordance with a modulation mode, a hop time and a valid symbol time per hop of an input signal; calculating an output sampling rate of the input signal based on the number chips per hop and the valid symbol time per hop; calculating a number samples per chip based on the input sampling rate and the output sampling rate, and a number samples per hop based on the input sampling rate and the hop time, respectively; determining a discrete Fourier transform (DFT) size less than the number samples per chip; calculating a channel spacing of the input signal based on the input sampling rate and the discrete Fourier transform (DFT) size; determining a number of valid output channels of the input signal based on the input channel group bandwidth and the channel spacing; determining a number of data samples of the input signal and which data samples are to be blanked on either side of a chip boundary based on the number samples per hop and the number chips per hop; and determining a:circular shift value based on the sample number modulo the discrete Fourier transform (DFT) size, where the sample number is from zero to the number samples per hop minus one.
The number of data samples of an input signal to be blanked, the circular shift value, and the discrete Fourier transform (DFT) size are then used to construct a single orthogonal channelizer comprising a blanking filter and cyclic shift block which performs sample blanking operations in accordance with the number of data samples of said input signal to be blanked, and phase shift operations in accordance with the circular shift value, and a discrete Fourier transform (DFT) block which performs discrete Fourier transform (DFT) computations in accordance with the DFT size. The single orthogonal channelizer obtained using the innovative channelizer design methodology of the present invention is provided for efficiently servicing multiple input data rates with minimal additional hardware for reconfiguration while realizing design hardware savings. The configurable orthogonal channelizer may be implemented with an efficient hardware architecture using blanking filter, cyclic shift and discrete Fourier transform techniques to separate an input signal of different channel group bandwidths into a plurality of individual channels at different data rates. The orthogonal channelizer can be configurable to separate data samples of an input signal into a first plurality of individual channel(s) with a spacing of a bandwidth frequency of the input signal at a first data rate using sample blanking operations, cyclic shift operations and discrete Fourier transform (DFT) computations, when a selected mode of channelization corresponds to the first data rate. Similarly, the single orthogonal channelizer can also be configurable to separate data samples of the input signal into a second plurality of individual channel(s) with a spacing of twice a bandwidth frequency of the input signal at a second data rate using sample blanking operations, cyclic shift operations and selected discrete Fourier transform (DFT) computations, when a selected mode of channelization corresponds to the second data rate. Likewise, the single orthogonal channelizer can further be configurable to separate data samples of said input signal into a third plurality of individual channel(s) with a spacing of four times a bandwidth frequency of the input signal at a third data rate using sample blanking operations, cyclic shift operations arid selected discrete Fourier transform (DFT) computations, when a selected mode of channelization corresponds to the third data rate.
In accordance with another aspect of the present invention, a configurable orthogonal channelizer obtained using the innovative channelizer design methodology is provided with a blanking filter and cyclic shift block comprising memory devices and serial-to-parallel registers, arranged in parallel to receive successive sets of data samples of an input signal of an input sampling rate, which performs blanking operations in which a predetermined number of data samples on either side of a modulator transition are blanked for guard time, and which performs phase shift operations in accordance with a number of shifts determined by (sample number)*modulo (DFT size), where a sample number from zero to the total number samples per hop to produce phase adjusted outputs; and a discrete Fourier transform (DFT) block arranged in parallel to receive respective ones of the phase adjusted outputs, which performs discrete Fourier transform (DFT) computations to produce individual channels at a different data rate.
The blanking filter and cyclic shift block may contain a first memory device which receives a sequence of real data for sample processing; a second memory device which receives a sequence of imaginary data for sample processing; a first serial-to-parallel register which passes processed samples of cyclically shifted real data from the first memory device as parallel sample outputs while discarding blanked samples; a second serial-to-parallel register which passes processed samples of cyclically shifted imaginary data from the second memory device as parallel sample outputs while discarding blanked samples; and a control logic block which incorporates blanking and cyclic shifting when addressing and retrieving real and imaginary data input from the first and second memory devices respectively.
The discrete Fourier transform (DFT) block may contain multiplexers for arranging the complex data according to the DFT size so that the input and the output ordering of the DFT points will be corrected; first 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of phase adjusted outputs of real data, which perform 4-point transformations to produce first transform outputs of complex data; second 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the phase adjusted outputs of imaginary data, which perform 4-point transformations to produce second transform outputs of complex data; first combine 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the first transform outputs of complex data, which combine 4-point transformations to produce first combined outputs of complex data; second combine 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the second transform outputs of complex data, which combine 4-point transformations to produce second combined outputs of complex data; and combine 8-point discrete Fourier transform (DFT) units, arranged to receive the first and second combined outputs of the complex data to produce individual channels of interest.
In accordance with yet another aspect of the present invention, a configurable orthogonal channelizer obtained using the innovative channelizer design methodology is provided with a plurality of memory devices and serial-to-parallel registers, a plurality of multiplexers, and a plurality of discrete Fourier transform (DFT) units arranged in parallel to perform sample blanking and phase shift operations and discrete Fourier transform (DFT) computations to separate an input signal into individual channels with a channel spacing of a bandwidth frequency at a 1xc3x97data rate, when a selected mode of channelization indicates the 1xc3x97data rate. However, when the selected mode of channelization indicates a 2xc3x97data rate, first selected ones of the discrete Fourier transform (DFT) units are bypassed while other hardware implementations operate together to separate data samples of an input signal into individual channels with a spacing of twice the bandwidth frequency at the 2xc3x97data rate. Likewise, when the selected mode of channelization indicates a 4xc3x97data rate, second selected ones of the discrete Fourier transform (DFT) units are bypassed while other hardware implementations operate together to separate data samples of an input signal into individual channels with a spacing of four times the bandwidth frequency at the 4xc3x97data rate.
The memory devices may be used to receive a sequence of real and imaginary data of the input signal for sample processing. The serial-to-parallel registers may be used to pass processed samples of cyclically shifted real and imaginary data of the input signal from the memory devices as parallel sample outputs while discarding blanked samples.
The multiplexers may be arranged in parallel to receive respective ones of the parallel sample outputs of cyclically shifted real and imaginary data of the input signal, which shuffle the data to achieve correct ordering at the input to the DFT in accordance with the DFT size chosen, which is in accordance with the data rate of the output channels.
The discrete Fourier transform (DFT) units may contain first 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of phase adjusted outputs of real data, which perform 4-point transformations to produce first transform outputs of complex data; second 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the phase adjusted outputs of complex data, which perform 4-point transformations to produce second transform outputs of complex data; first combine 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the first transform outputs of complex data, which combine 4-point transformations to produce first combined outputs of complex data; second combine 4-point discrete Fourier transform (DFT) units, arranged to receive respective ones of the second transform outputs of complex data, which combine 4-point transformations to produce second combined outputs of complex data; and combine 8-point discrete Fourier transform (DFT) units, arranged to receive the first and second combined outputs of the complex (real and imaginary) data to produce individual channels of interest. The present invention is more specifically described in the following paragraphs by reference to the drawings attached only by way of example.